1. Technical Field
The present invention relates to semiconductor integrated circuits in general, and in particular to domino logic circuits. Still more particularly, the present invention relates to a domino logic circuit having a multiplicity of gate dielectric thicknesses.
2. Description of the Prior Art
Domino logic circuits are commonly found in integrated circuits. A domino logic circuit simplifies digital logic by connecting a number of transistors together in series to implement digital combination logic. For example, a domino logic circuit implements a logic AND function by simply cascading a P-channel transistor with several N-channel evaluate transistors in series. During operation, the P-channel transistor is clocked to precharge an output node of the circuit to a predetermined logic state. Depending on the logic state at the inputs of the N-channel input transistors, the output node either remains at its precharged state or is pulled low through the series of N-channel input transistors by a clocked N-channel transistor connected to ground.
In recent years, the predominant processing technology for manufacturing integrated circuits has been the complementary metal oxide silicon (CMOS) technology. Although CMOS technology offers various advantages, such as low power consumption and stability, over other types of processing technologies, one major drawback of CMOS circuits is their relatively slow speed. While device scaling may improve the speed of CMOS domino logic circuits, the degree of scaling is limited by the minimum allowable thickness of the gate dielectric of a transistor before electron and/or hole tunnelling between the gate electrode and the channel presents a prohibitively large current when the transistor is turned on. The present disclosure describes an improved domino logic circuit that can overcome the above-mentioned problem.
A domino logic circuit includes a precharge transistor, an isolation transistor, and multiple evaluate transistors. The precharge transistor, which is connected between the power supply and a dynamic node, receives a clock input. The isolation transistor is connected to ground and also receives the clock input. Each of the input transistors, which are coupled between the precharge transistor and the isolation transistor, receives a signal input. In accordance with a preferred embodiment of the present invention, the gate dielectric thickness of the evaluate transistors and the isolation transistor is less than the gate dielectric thickness of the precharge transistor.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.